搜索资源列表
mulhoulai
- 这是一个乘法器的Verilog实现,这是仿真AMR处理器核中的乘法器开发的。挺不错的。-It is a multiplier using the Verilog.
chengfaqi.doc
- 设计一个两个5位数相乘的乘法器。用发光二极管显示输入数值,用7段显示器显示结果。乘数和被乘数分两次输入(verilog语言实现)-Design a multiplier of two 5-digit multiplication. Enter the value with the light-emitting diode display, with 7-segment display shows the results. Multiplier and the multiplicand input
ff_mul
- 基于rs编码器的verilog伽罗华域乘法器设计-Rs encoder based on Galois field multiplier verilog
ff_const_mul
- 常系数有限域乘法器,verilog DHL源码-Constant coefficient finite field multiplier, verilog DHL source
72
- 7:2乘法器 ,应用verilog语言 ,快速高效,使用了华莱士树-Dragging on time-multiplier, application verilog language, fast and efficient, the use of the Wallace tree
Multiplier
- 时序乘法器,verilog编写,速度慢,但消耗资源少,时钟沿到来时,输入/输出1bit数据-Sequential multiplier, verilog written, slow, but consume fewer resources, the clock edge arrives, the input/output 1bit data
multiplier
- 压缩的乘法器。是基于VERILOG 语言实现的,有较快的速度。-Compression of the multiplier. Is based on the VERILOG language, there is a faster speed.
mul_ser12
- 本源码是用Verilog编写的12位移位相加乘法器的设计源码,开发软件为MAX+PLUS,已经测试通过。-The Verilog source code is written in the sum of 12-bit shift multiplier design source code, developing software for the MAX+ PLUS, has been tested.
add_tree_mult
- verilog HDL编写的8位乘法器,谢谢使用-the preparation of 8-bit multiplier verilog
24x24-booth
- 可用的24位x24位的booth乘法器的verilog代码-24X24 booth muplily
multiplierunit
- VHDL/FPGA/Verilog 实现乘法器的功能-use VHDL/FPGA/Verilog multiplier unit
mux1
- 利用verilog编写的一个乘法器,没有仿真,应该是对的。-this is a verilog cheng xu, cheng fa qi。mei you fang zhen
verilog_Common_arithmetic
- 常用逻辑运算,加法器,乘法器及除法器的verilog语言,可用modelsim或Quartus II 9.0环境-Common logic operation, adder, multiplier and divider verilog language, can be used modelsim or Quartus II 9.0 environment
MULTIPLE_CORE
- 硬件乘法器,其基础就是加法器结构,它已经是现代计算机中必不可少的一部分。[1]乘法器的模型就是基于“移位和相加”的算法。在该算法中,乘法器中每一个比特位都会产生一个局部乘积。第一个局部乘积由乘法器的LSB产生,第二个乘积由乘法器的第二位产生,以此类推。如果相应的乘数比特位是1,那么局部乘积就是被乘数的值,如果相应的乘数比特位是0,那么局部乘积全为0。每次局部乘积都向左移动一位。 -64-bit multiplier design experiment is the first in the HK
mult
- 用verilog HDL语言实现的16位乘法器,以及tesrbench(测试文件)。-Verilog HDL language with 16-bit multiplier, and tesrbench (test file).
multiplier
- 几种verilog乘法器的代码,用于比较不同乘法器特点-Several multiplier verilog code, used to compare the different characteristics of the multiplier
verilog5
- 用verilog语言编写的4位乘法器程序。通过循环移位进行4位二进制数的乘法运算。压缩包内也包含此4位乘法器程序的modelsim仿真文件。-Verilog language with 4-bit multiplier process. By cyclic shift for 4-bit binary number multiplication. This compressed package also contains four multipliers modelsim simulation
booth_mult
- 布斯乘法器的verilog实现及仿真文件,使用modelsim仿真-booth mult s verilog and test
lut_mult
- 基于查找表的乘法器实现,verilog编写,Modelsim测试-use lut realize the mult
mul1617
- 采用verilog RTL级语言,实现了有符号的16位乘17位的乘法器。特点是:采用流水的结构,可以在一个周期内处理完数据。通过QuartusII和Modulesim的功能仿真和时序仿真,并得到正确结果。-Realize the signs of 16 of the 17 patients take on time-multiplier. Features are: the structure of water, can be in a cycle processes the data. Thr